In digital circuits many times it is necessary to have all signals synchronized with a common clock signal (i.e., the system clock signal). A problem arises when a signal needs to be phased to the system clock signal but the signal phase with respect to the system clock is arbitrary. If the signal phase is arbitrary, a possible setup or hold violation exists. That is to say, a transition of an information signal may occur relative to a transition of the system clock signal such that the information signal does not satisfy the time requirements of a storage circuit (e.g., flip-flop). These time requirements require the signal to be stable for a predicted interval immediately prior to (setup) and immediately subsequent to (hold) the active clock edge to ensure that the data is stored in the flip-flop. Violating these time requirements, which effectively means the data input signal and the clocking signal transition within close proximity of one another, can lead to the flip-flop entering an uncertain and unstable state known as metastability. This, in conjunction with the fact that there is almost always some jitter in the signal to be clocked, can cause the signal to be clocked on two possible clock edges. This may cause the digital system to react in an undesired manner.
In at least one attempt to address this problem, an analog phase comparator has been used to measure the phase difference between the signal and clock. This analog measurement is used to determine how to synchronize the reference signal to the clock signal.